1. Technical Field
The present invention relates to a fringe field switching (hereinafter, referred to as “FFS”) mode liquid crystal display (LCD) panel. More particularly, the present invention relates to an FFS mode LCD panel in a dual-domain structure in which pixels are arranged in a delta arrangement.
2. Related Art
In recent years, LCD panels are widely used not only for information and communication devices but also for electrical devices in general. Typical LCD panels include one pair of substrates made of glass and the like formed with electrodes and the like on their surfaces, and a liquid crystal layer formed between the pair of substrates. By applying a voltage to the electrodes on both substrates to change transmittance of light by rearranging liquid crystal molecules, various images are displayed. This is a so-called longitudinal electric field mode. There are a twisted nematic (TN) mode and a vertical alignment (VA) mode in a longitudinal electric field mode LCD panel. But, as there is a problem of a narrow viewing angle, various improved longitudinal electric field mode LCD panels such as a multidomain vertical alignment (MVA) mode have been developed.
Unlike the above longitudinal electric field mode LCD panel, an LCD panel including electrodes only on one of the substrates, which may be called a transverse electric field mode, is known as an in-plane switching (IPS) mode LCD panel (refer to JP-A-2005-338256). An operational principle of the IPS mode LCD panel will be described with reference to FIGS. 11 and 12. FIG. 11 is a schematic plan view of one pixel of the IPS mode LCD panel, and FIG. 12 is a schematic sectional view taken along the line XII-XII of FIG. 11.
An IPS mode LCD panel 50 includes an array substrate AR and a color filter substrate CF. The array substrate AR is provided with a plurality of scanning lines 52 and common lines 53 in parallel on a surface of a first transparent substrate 51. A plurality of signal lines 54 are provided in a direction perpendicular to the scanning lines 52 and the common lines 53. In a central part of each pixel, a strip of common electrode 55 is provided from the common line 53, in an inverted T-shape as in FIG. 11. A pixel electrode 56 is provided so as to surround the periphery of the common electrode 55.
A thin film transistor (TFT) serving as a switching element is formed between the scanning line 52 and the signal line 54. The TFT is disposed with a semiconductor layer 57 between the scanning line 52 and the signal line 54. A portion of the signal line on the semiconductor layer 57 forms a source electrode S, a portion of the scanning line under the semiconductor layer 57 forms a gate electrode G, and a portion of the pixel electrode 56 overlapping with a part of the semiconductor layer 57 forms a drain electrode D.
The color filter substrate CF includes a color filter layer 59 on a surface of a second transparent substrate 58. The array substrate AR is disposed to face the color filter substrate CF, so as the pixel electrode 56 and the common electrode 55 of the array substrate AR, and the color filter layer 59 of the color filter substrate CF are opposed to each other. A liquid crystal LC is sealed therebetween. By respectively disposing polarizers 60 and 61 at outer sides of both substrates, so that their polarizing directions are perpendicular to each other, the IPS mode LCD panel 50 is formed.
According to the IPS mode LCD panel 50, as shown in FIG. 12, when an electric field is formed between the pixel electrode 56 and the common electrode 55, liquid crystal molecules aligned in a horizontal direction revolve in a horizontal direction. This enables the amount of transmitting light entering from a backlight to be controlled. The IPS mode LCD panel 50 has a wide viewing angle and high contrast. Furthermore, because the pixel electrode 56 and the common electrode 55 are disposed with a relatively narrow space therebetween, it has an advantage of secondarily generating a storage capacitance. But, because the common electrode 55 is formed of the same metal material as the common line 53, there are problems of a low aperture ratio and a low transmittance, and color changes depending on viewing angle.
In order to solve the problems of the low aperture ratio and the low transmittance of the IPS mode LCD panel, an FFS mode LCD device which may be called an inclined electric field system has been developed (refer to JP-A-2000-131720, JP-A-2002-14363 and JP-A-2002-244158). An operational principle of such a FFS mode LCD panel will be described with reference to FIGS. 13 and 14. FIG. 13 is a schematic plan view of one pixel of an FFS mode LCD panel, and FIG. 14 is a schematic sectional view taken along the line XIV-XIV of FIG. 13.
An FFS mode LCD panel 70A includes an array substrate AR and a color filter substrate CF. The array substrate AR is provided with a plurality of scanning lines 72 and common lines 73 in parallel on a surface of a first transparent substrate 71. A plurality of signal lines 74 are provided in a direction perpendicular to the scanning lines 72 and the common lines 73. A common electrode 75 made of a transparent material such as indium tin oxide (ITO), which is connected to the common line 73, is provided so as to cover an entire surface of each pixel. A pixel electrode 78A made of a transparent material such as ITO, which is formed with a plurality of slits 77A in stripes, is provided on a surface of the common electrode 75 with an insulating film 76 therebetween.
A TFT serving as a switching element is formed near an intersection of the scanning line 72 and the signal line 74. The TFT is disposed with a semiconductor layer 79 on a surface of the scanning line 72. A part of the signal line 74 is extended to cover a part of a surface of the semiconductor layer 79, thereby forming a source electrode S of the TFT. A portion of the scanning line under the semiconductor layer 79 forms a gate electrode G, and a portion of the pixel electrode 78A overlapping with a part of the semiconductor layer 79 forms a drain electrode D.
The color filter substrate CF includes a color filter layer 81 on a surface of a second transparent substrate 80. The array substrate AR is disposed to face the color filter substrate CF, so as the pixel electrode 78A and the common electrode 75 of the array substrate AR, and the color filter layer 81 of the color filter substrate CF are opposed to each other. A liquid crystal LC is sealed therebetween. By respectively disposing polarizers 82 and 83 at outer sides of both substrates, so that their polarizing directions are perpendicular to each other, the FFS mode LCD panel 70A is formed.
According to the FFS mode LCD panel 70A, when an electric field is formed between the pixel electrode 78A and the common electrode 75, as shown in FIG. 14, the electric field moves toward the common electrode 75 from both sides of the pixel electrodes 78A. This allows not only liquid crystal molecules existing between the pixel electrodes 78A but also liquid crystal molecules existing above the pixel electrodes 78A to move. Therefore, the FFS mode LCD panel 70A has a wider viewing angle and higher contrast than the IPS mode LCD panel 50, and allows a bright display because of its high transmittance. In addition, the FFS mode LCD panel 70A has an advantage of secondarily generating a larger storage capacitance, because the overlapping area between the pixel electrode 78A and the common electrode 75 is larger than that in the IPS mode LCD panel 50 in plan view, thereby eliminating a need to provide an auxiliary capacitor line separately.
According to the FFS mode LCD panel, in the same manner as the IPS mode LCD panel disclosed in JP-A-2005-338256, due to its display characteristics, a rubbing direction is preferably perpendicular to the signal lines, and a minimum inclined angle is preferably provided between the pixel electrodes and the rubbing direction. Therefore, as an FFS mode LCD panel 70B shown in FIG. 15, slits 77B in stripes provided to a pixel electrode 78B are inclined toward the scanning line 72 or the common line 73. Similarly, in order to eliminate changes in color depending on viewing angle, as an FFS mode LCD panel 70C shown in FIG. 16, a dual-domain approach has been adopted by disposing slits 77C in stripes provided to a pixel electrode 78C in a V-shape. The only difference between the FFS mode LCD panels 70B and 70C shown in FIGS. 15 and 16, and the FFS mode LCD panel 70A shown in FIG. 13, is the inclination of the slits 77B or 77C provided to the pixel electrode 78B or 78C. The same components of the panels 70B and 70C as in the panel 70A shown in FIG. 13 are denoted by the same reference numerals, and descriptions thereof are omitted.
As described above, FFS mode LCD panels have a wider viewing angle and higher contrast than IPS mode LCD panels, and allow a bright display because of their high transmittance. As they can operate at low voltage and secondarily generate a larger storage capacitance, their display quality is excellent even when an auxiliary capacitor line is not provided separately. In the FFS mode LCD panels disclosed in JP-A-2000-131720, JP-A-2002-14363 and JP-A-2002-244158, pixels are aligned in a row direction and a column direction, and generally used in combination with color filers arranged in stripes or color filters arranged in diagonal rows. When they are used mainly for displaying images taken by a digital still camera and the like, a delta arrangement (also referred to as “triangle arrangement”), in which pixels are arranged alternatively, may be used.
According to these FFS mode LCD panels in which pixels are arranged in the delta arrangement, the shape of the slits is preferably formed in the same shape at every pixel electrode in order to reduce display unevenness. However, the signal lines need to be arranged in a direction perpendicular to the scanning lines, although in a crank manner, by shortening the wiring length. As a result, the TFTs are positioned differently depending on whether they are in odd-numbered or even-numbered rows. Such a state will be described with reference to FIG. 17. FIG. 17 is a schematic plan view of several pixels of an FFS mode LCD panel 70D in which pixels are arranged in a delta arrangement. The view shows a pixel electrode 78D and slits 77D provided at the pixel electrode 78D only, omitting other specific features. In FIG. 17, broken lines between the pixels show a boundary of each pixel, and solid lines show a path of the signal line. A portion enclosed within a broken line circle shows a position where the TFT of each pixel is provided.
In the FFS mode LCD panel 70D shown in FIG. 17, the TFTs of the pixels in odd-numbered rows are positioned at the lower right-hand side of the view, while the TFTs of the pixels in even-numbered rows are positioned at the lower left-hand side of the view, whereby the signal lines can be arranged linearly in a longitudinal direction, although in a crank manner, with a short wiring length. In the FFS mode LCD panel 70D, the shape of slits provided to each pixel electrode of the pixels in odd-numbered row are formed in an optimum shape to utilize a display opening effectively. But, the shape of the slits provided to each pixel electrode in even-numbered rows at a position shown by the X-mark in the view is different from that of odd-numbered rows. As they cannot form into the same shape, a symmetrical viewing angle cannot be obtained. As a result, when the FFS mode LCD panel 70D displays an image, spots are generated in a transverse direction. On the other hand, when the shape of the slits of the pixel electrode of each pixel is made into the same shape both in odd-numbered and even-numbered rows, the display opening cannot be effectively utilized. The same phenomenon occurs to FFS mode LCD panels having slits provided to the pixel electrodes in a dual-domain structure and pixels provided in a delta arrangement.